Dark Posted February 18, 2021 Posted February 18, 2021 (edited) One of the biggest problems in computing today is the so-called "memory wall," the difference between processing time and the time it takes to send data to the processor from memory chips. The growing po[CENSORED]rity of AI applications has only made that problem more pronounced, because huge networks that find faces, understand speech, and recommend consumer goods rarely fit on a processor's onboard memory. Now separate research groups from the US and Belgium believe that a new type of zero-latency DRAM could be the solution, and here's how it works. The new DRAM, made of oxide semiconductors and built in layers above the processor die (that is, integrated), retains hundreds or thousands of times more bits than commercial DRAM and could provide significant area and power savings , especially running large neural networks. How Zero Latency DRAM Works The DRAM memory cells in your PC are made of a single transistor and a single capacitor each in a design called 1T1C. To write a bit to the cell the transistor is turned on and the charge is pushed towards (1) or removed from (0) the capacitor. To read from it, the charge (if any) is removed and measured; it is a very fast, cheap and low power consumption system but it has some disadvantages: on the one hand, reading the bit depletes the capacitor so it has to be written back to memory and in fact even if the bit is not read the charge will eventually leak out of the capacitor through the transistor. So all cells need to be updated periodically just to be able to keep data, and in modern chips this is done every 64 milliseconds. DRAM-chips-01 Embedding DRAM on the processor chip itself is done commercially, but it has its limits. The challenge with the 1T1C monolithic design has always been the difficulty of building the capacitor, as well as making a non-leaking transistor using the manufacturing process intended for logic transistors. Good capacitors are difficult to make in manufacturing processes created for logic circuits. Instead, the new built-in DRAM is made of just two transistors and uses no capacitor (2T0C), and this works because the gate of a transistor is a natural capacitor, albeit a small one. So the payload the bit represents can be stored there, and this design has some key benefits, especially for AI. 2T0C DRAM Circuit One of these advantages is that writing and reading involves doing it on separate devices, and therefore can be read from a DRAM 2T0C cell without destroying the data and having to write it again. All you have to do is see if the current flows through the transistor whose gate holds the charge, and if it is there, it will turn the transistor on, the current flows, and if there is no change it stops. This is a zero latency read, and it is especially important for AI because neural networks tend to read at least three times for every write. However, a 2T0C arrangement does not work well with silicon logic transistors, and any bits would immediately drain because the transistor gate capacitance is too low and the leakage through the transistors is too high. So researchers have turned to devices made from amorphous oxide semiconductors, such as those used for the pixels in some displays. A new manufacturing method for a new DRAM These types of materials have some especially useful qualities for DRAM. In particular, they can carry a lot of current, which makes writing faster, and when they are off they lose very little charge, which makes the bits last longer. The US-based team used Indium Oxide doped at about 1% with Tungsten (IWO) as its semiconductor. The currents in this type of device provide sufficient read and write speed sufficient for logical operations, and at the same time the shutdown currents are really small, on the order of two or three times less than with Silicon. Edited February 18, 2021 by -Dark
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