[Hardware] AMD shows how it will connect its chiplets in GPU: Last Level Cache arrives

[WilkerCSBD]

It cannot be classified as a secret, since everyone is jumping, but AMD is going to go directly to the graphics market in one or two more generations, at the latest. What was revealed today is from last Thursday and shows a registered patent said day 1 where Lisa Su's already have planned how to connect chiplets: Unified Last Level Cache arrives.

Chiplets are the future of both CPUs and GPUs, where the problem as we already know is the interconnections between them and the resources that AMD, Intel and NVIDIA leave to share between them. The patent tries to explain how AMD would launch a state-of-the-art shared memory resource that in turn would be unified for everyone, a design very similar to what we saw in Zen 3.

A unified, shared and modular architecture: Unified Last Level Cache
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In the details is what is important and although the explanation above summarizes what Lisa Su's plan, the truth is that if we look closely at the patent it leaves open the possibility of an "N" number of chiplets. This is important, because it assumes that this new technology will be the cornerstone of a future project that assumes that the number of chiplets will increase as the nodes allow it.

However, there is one concept that is not fully defined: Primary GPU Chiplet. As can be seen in the slides, it will be the cached data that determines and goes to the "Active Bridge Chiplet" or the "Caching Chiplet", implying that as in Zen architectures we would have a supposed I / O die called Bridge Active Chiplet.

It is this that distributes the tasks for the GPU chiplets through their memory channels and through the Unified Last Level Cache. That is, instead of having independent chiplet caches as if they were CPU cores with their L1 and L2 cache, AMD with this specific chiplet would act as a monolithic cache.

Addressable memory, a single top-level cache, and logs
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The play seems well marked: not making the programmers have to change all their software and way of working to compile the loads to the chiplets individually. On the contrary, with this the developers do not have to take into account if we are talking about 1, 2 or 20 chiplets, since it is the Active Bridge Chiplet that is responsible for distributing the loads and work.

Therefore LLC would be like a kind of L3 in the purest Infinity Cache style, so we do not know if this will keep or change its function or simply take a new approach while maintaining its essence.

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In any case, AMD is going for the graphics card market, now it remains to be seen if we are facing a blow for data centers and AI, for gaming GPUs or for both as a fundamental piece of chiplet design within the company.

What we do know from the January patents is that the design is very advanced and although these patents are simple diagrams, the work on the design table is finished, so it should not take too long to start with the real tests for these designs, if they are not already in it ...