[Hardware] Intel lists 30 million Tiger Lake CPUs at 10nm, is it possible?

[UltimaTexCS]

Tiger Lake is without a doubt the great unknown in general terms of performance and availability. Although it is going to dedicate itself exclusively to the notebook sector, Intel has explained that so far it has a whopping 30 million Tiger Lake chips available, something really striking and that seen the performance in wafers of its 10 nm has collided head-on with his previous statements. How many wafers are required per day for that many chips? Is this figure really possible?

The figure of 30 million CPUs manufactured scares, let's reflect, 30 million chips ready to be shipped. Knowing that in the worst case the die measures 13.49 x 10.70 mm we can calculate how many chips Intel can manufacture in a 12-inch wafer, therefore and knowing the performance of the company's scanners, we can know how many die per hour and day they manufacture. Does Intel tell the truth?

Intel Tiger Lake, more time than discussed in production?
Intel Tiger Lake

The figures are really surprising if we take them in their computation, and it is that with wafer calculator in hand and those dimensions, Intel could be manufacturing about 400 dies per 12-inch wafer, that is, 400 chips per wafer.

If performance were perfect, which it is not, Intel would have needed more than 75,000 wafers in total to bring those functional chips to life. Therefore, and giving an estimate of error in the engraving of the wafers of 0.2, the most realistic approximation could be between 350 and 300 chips ready to be sold.

Let's take the lowest figure being less optimistic, 300 chips per 12-inch wafer, Intel would have needed approximately and rounding 100,000 wafers. The problem is that the estimates are quite higher: between 120k and 150k of wafers. Is this possible for the three high-performance 10nm SuperFin FABs that Intel has at full performance?

The density of the defect could be higher, which would imply higher prices
intel-boyd-phelps-tiger-lake-wafer

If we raise the density of the defect to 0.3 per cm2 what we will obtain is precisely a number of wafers similar to that specified above, but at the same time we have to take other data into account. The 10nm SuperFin are being used by the new Ice Lake Xeons, which are widely expected by companies and Intel has reserved a lot of capacity for months.

Ergo, according to official data, Intel would be launching 130k wafers at 10 nm per month, very close to what we have mentioned, so if you reserve production for Ice Lake… Is the figure of 30 million chips possible for Tiger Lake? At an average of 20,000 wafers a month, 645 wafers a day and assuming that Intel has ASML scanners that could do 125 WPH, we would be facing a much lower performance than they say or a much longer time to manufacture that many chips.

And it is that, to understand us, at full performance and with the density of TSMC for its 7 nm, Intel could be manufacturing up to 3000 wafers a day and not 645, so the performance is much lower than expected and the chips are surely much smaller per wafer. Therefore, the price per unit could be really high and hence also the constant rise in price of laptops.

The numbers do not add up or there is a problem in another BEOL or FEOL process that they are not telling us, in any case, it seems that production has been underway for months, so it is possible that there will be no shortage of CPUs in laptops if all this is fulfilled.